The present invention relates to a wafer-level packaging process for MEMS applications, and more specifically, to a method for putting electrical feed-throughs through an SOI wafer.
In microelectromechanical systems (MEMS), the functional element, such as a circuit, sensor or actuator, must often be separated from the environment, yet electrical signals must be sent to and received from the functional element. The functional elements are flexible structures operable within a hermetically sealed cavity. The challenge in packaging MEMS is achieving the electrical connection without opening the cavity to the environment, and to do this with a simple process that results in a small overall footprint and outline. In other words, the MEMS should be fabricated to form a functional element within a hermetically sealed cavity in the semiconductor wafer having an overall structure of small dimension both laterally and vertically.
Past and current attempts to achieve such MEMS include die-level hermetic packaging, but this method produces a device with a large package size at a high cost. Another example is a buried feed-through, but this is a relatively complex process. Still another example is first bonding, then sealing open areas with high temperature LPCVD films, but high temperature processing is not compatible with many metals present on the wafers.
A need thus exists in the semiconductor industry for a method for wafer-level packaging for MEMS applications that allow small footprints, small chip outlines, low-temperature processing, hermetic sealing, and low cost.
The present invention provides a wafer-level packaging process for MEMS applications in which a SOI (silicon-on-insulator) wafer is bonded to a MEMS wafer and the electrical feed-throughs are achieved through the SOI wafer. The process of the present invention is a simple procedure involving no high temperatures and results in a small, thin device with functional elements hermetically sealed therein. To this end, the method includes providing a first substrate having the functional element thereon connected to at least one metal lead, and providing a second SOI substrate having a recessed cavity in a silicon portion thereof with metal connectors formed in the recessed cavity. The non-recessed surfaces of the second SOI substrate are bonded to the first substrate to form a hermetically sealed cavity. Within the cavity, the metal leads are bonded to respective metal connectors. Prior to bonding, the recessed cavity has a depth that is greater than the thickness of the functional element and less than the combined thickness of the metal leads and their respective metal connectors. After bonding, silicon from the second SOI substrate is removed to expose the buried oxide portion of the second SOI substrate. Metal pads are then formed through the second SOI substrate to the metal connectors within the cavity, such as by etching vias in the substrate and depositing the metal pads within the vias. Wire bond pads are thereby connected to the functional element without opening the cavity to the environment. Electrical signals may then be fed through the SOI wafer to the metal connectors, metal leads and the functional element. In one embodiment of the method of the present invention, an oxide layer is grown on the SOI wafer both on the surface to be bonded to the first substrate and within the recessed cavity to provide electrical isolation between electrical connectors. In yet another embodiment of the method of the present invention, a passivation layer is applied over the buried oxide layer of the SOI substrate and over the metal pads.